AISHWARYA SINGH
E-mail: singhaishwarya1977@gmail.com
Cell
No.: +1 (385) 775-2699, +1 (239) 205-4843
EDUCATIONAL QUALIFICATION
· BE (Electronics and Telecommunication),
PVG’s College of Engineering and Technology, University of Pune (India), May
2000
· Postgraduate Diploma in VLSI Design,
Pune Institute of Computer Technology (PICT-SITM), Pune (India), August 2003
PROFILE
· 12 years of experience in VLSI Frontend Design
· In depth knowledge in Digital Circuit Design Concepts
· Hands-on experience in RTL design using Verilog
· Ability to work in a team and as an individual
· An effective team player with excellent planning and
execution skills coupled with a systematic approach and quick adaptability
· Hands on experience in chip bring-up at Huawei – China
(FPGA) and Lantiq – Germany (ASIC)
PROFESSIONAL EXPERIENCE
|
Designation
|
Organization
|
Start Date
|
End Date
|
|
Principal Engineer
|
Broadcom Corporation, India
|
May ‘14
|
Present
|
|
Staff Engineer
|
Lantiq Communications, India (previously
Infineon Technologies)
|
Nov ‘09
|
May ‘14
|
|
Sr. Design Engineer
|
Infineon Technologies, India
|
Sep ‘06
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Nov ‘09
|
|
Design/Verification Engineer
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LSI Logic, India
|
Apr ‘05
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Sep ‘06
|
|
Design Engineer
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IshnaTek Systems, India
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Aug ‘03
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Apr ‘05
|
|
Project Engineer
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HCL Technologies, India
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Dec ‘00
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Jul ‘01
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AWARDs
and RECOGNITIONS
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Spot Award
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Design Lead for the Conv+ project at
Lantiq Communications, India
|
|
Recognition
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Annual team award for IVE1000 project at
Lantiq Communications, India
|
|
Recognition
|
Annual team award for Conv+ project at
Lantiq Communications, India
|
PROJECTS
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Project
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Hash Tables (Data Center Switch)
|
|
Synopsis
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A hash table database entry is comprised
of Key and Associated Data. The main function of the hash table is to
compare a Search Key against the Table Entry Keys looking for an exact
match. If an exact match is found the associated data along with the matching
key is returned
|
|
Responsibility
|
·
Understanding
the existing architecture/design and updating the size of all the hash
tables
·
Implementation
of 3 new features:
o Supporting 2 simultaneous reads on SPRAMs
o Reducing the sizes of the hash tables by half, when the
bond option is applied
o Common module for the Design Observation Points (DOP)
functionality for both the ingress and egress directions
·
Bug and
timing fixes
·
Line/Conditional
coverage
·
RTL changes
for fixing of setup violations
|
|
Language, Tool
|
Verilog
|
|
Project
|
IVE 192
|
|
Synopsis
|
The chip performs dual functionality i.e.
Converter Chip and Vectoring. The vectoring (cancellation) is performed in
both the upstream and downstream directions. The supported profiles are 17
and 30. Full cancellation of 64 ports is done for profile 17 and 32 ports
for profile 30.
|
|
Responsibility
|
·
Micro-architecture
development
·
Coding of
the entire Converter chip functionality in the Execution Unit (EU).
·
Coding of
certain modules for the Vectoring functionality in the EU.
·
Team leader
(Team Size = 7)
|
|
Language, Tool
|
Verilog, VHDL (module top level
integration), NC-Verilog
|
|
Project
|
Test Chip Development
|
|
Synopsis
|
The chip is used for testing of the
Analog blocks like the DAC, ADC and the PLLs. To support this, the digital
portion is developed having DAC/ADC ports interfaced between a 256Kbyte RAM
and the analog design.
|
|
Responsibility
|
·
Micro-architecture
development
·
Coding of
the digital portion of the test chip and integration of all the blocks on
the top level
·
Team leader
(Team Size = 1)
|
|
Language, Tool
|
Verilog, VHDL (chip top level
integration), NC-Verilog
|
|
Project
|
Converter Chip - Conv+ (Xilinx Kintex-7
FPGA)
|
|
Synopsis
|
The converter FPGA operates in a system
consisting of a VDSL chip (processing on a DSL port-by-DSL port basis) and
a 3rd party vector
chip that runs vectoring algorithms (processing on “tone-by-tone” basis).
The converter chip does protocol conversion (Framing), data format
conversion (Tone ordering), data compression/decompression, final result
processing and synchronization. A total of 64 VDSL ports (Profile 17a) are
supported by this device.
|
|
Responsibility
|
·
Chip concept
and micro-architecture development of the High Speed Interfaces
(Proprietary 3GLP and XAUI)
·
Coding of
the proprietary 3GLP High Speed Interface (between VDSL chip and FPGA) and
the XAUI High Speed Interface (between FPGA and Vectoring chip)
·
Chip
bring-up activity at the customer site in Shenzhen (China)
·
Team leader
(Team Size = 3)
|
|
Language, Tool
|
Verilog, VHDL (module top level
integration), NC-Verilog
|
|
Project
|
Vector Engine (IVE 1000)
|
|
Synopsis
|
The chip performs vectoring
(cancellation) in both the upstream and downstream directions. The
supported profiles are 17 and 30. Full cancellation of 48 ports is done for
profile 17 and 32 ports for profile 30. There are 10 HSIFs each providing a
10Gbps data throughput
|
|
Responsibility
|
·
Micro-architecture
development of the High Speed Interfaces (Proprietary 3GLP and XAUI)
·
Coding of
the proprietary 3GLP High Speed Interface (between VDSL chip and Vector
Engine) and the XAUI High Speed Interface (between Vector Engines)
·
Chip
bring-up activity at the HQ in Munich (Germany)
|
|
Language, Tool
|
Verilog, VHDL (module top level
integration), NC-Verilog
|
|
Project
|
ADSL/VDSL Chip
|
|
Synopsis
|
The chip is a 16 channel VDSL2 data pump
used in the CO side
|
|
Responsibility
|
·
Coding of
GMII interface between the MAC and the chip system bus for both the ingress
and egress directions
·
Coding of
Byte/Bit packing logic and the interface towards the QAM/Trellis
encoder/decoder
|
|
Language, Tool
|
Verilog, ModelSim
|
|
Project
|
Ethernet Switch for a VDSL Chip
|
|
Synopsis
|
The Switch-IP is a 3 port switch having 2
Ethernet ports and 1 CPU port connected to the chip system bus.
|
|
Responsibility
|
Following are the upgrades that are
implemented:
·
Per packet
setting of the CRC
·
Enhancement
of CPU port from 1Gbps to 2Gbps
|
|
Language, Tool
|
Verilog, ModelSim
|
|
Project
|
Network Processor
|
|
Synopsis
|
It is a NWP on line cards of Ethernet
based DSLAMs. It provides direct connectivity between a DSL chipset and an
Ethernet PHY or SerDes, which drives the backplane
|
|
Responsibility
|
·
Specification
writing
·
Coding of
the SGMII (system side), SMII (system side) and SMII (line side) interfaces
for a network processor. The MAC for the above mentioned interfaces was
reused
·
Coding of
the interface between the MAC and the chip system bus
|
|
Language, Tool
|
Verilog, ModelSim
|
|
Project
|
SerDes Top Design
|
|
Technology
|
Soft IP
|
|
Synopsis
|
The SerDes Top is a wrapper on the SerDes
core, to configure SerDes core in different modes of operation
|
|
Responsibility
|
·
Specification
writing
·
RTL Coding,
verification and synthesis of the SerDes Top
|
|
Language, Tool
|
Verilog, ModelSim, Design Compiler
|
|
Project
|
IrDA Transmitter and Receiver Module
(Xilinx Vertex2 (XC2V1000) FPGA)
|
|
Synopsis
|
The module is interfaced with the PIC
microcontroller core. 8 bit data is taken from the PIC core, which is
first, converted into UART frame format and then is encoded so that it can
be sent across to the IR transmitter (analog part). The data that is
received from the IR receiver (analog) is first decoded, then converted
into UART frame format and then sent to the PIC core
|
|
Responsibility
|
·
Specification
writing and RTL Coding
|
|
Language, Tool
|
ModelSim, Synplify Pro, Xilinx Design
Manager
|
|
Project
|
PSL QA
|
|
Synopsis
|
Developing of the QA suite for testing
Solidify’s (limited) PSL support. The PSL constructs that did not function
as per the PSL LRM were reported as bugs to Averant
|
|
Responsibility
|
·
Creating
verilog test cases to cover all PSL constructs supported by the tool
|
|
Language, Tool
|
Verilog, Property Specification Language
(PSL), Solidify (Averant Inc.)
|
|
Project
|
Functional Static Verification of PCI –
Express bus protocol
|
|
Synopsis
|
The design is a PCIE to PCI Bridge. The
verification was of the Gray Box nature
|
|
Responsibility
|
·
Writing
properties for the configuration space header, different capabilities of
the device, the Data Link Layer
|
|
Language, Tool
|
Hardware Property Language (HPL),
Solidify (Averant Inc.)
|
|
Project
|
PIC16C54 Microcontroller IP (Xilinx
Vertex 2 and Actel APA075)
|
|
Synopsis
|
The design employs RISC architecture with
only 33 single word/single cycle instructions. All instructions are single
cycle except for program branches, which take two cycles. The instructions
are 12 bit wide. The core comprises of a serial interface that is used for
programming the internal RAM (512 X 12) with the user software. This serial
interface consists of Program, Verify and In Circuit Emulation modes
|
|
Responsibility
|
·
Involved in
the entire design of the Microcontroller
|
|
Language, Tool
|
Verilog, ModelSim, Synplify Pro, Xilinx
Design Manager, Libero
|
|
Project
|
ASICs & System Verification Project
for a Complex Optical Network system
|
|
Synopsis
|
This is a complex optical network system,
which can take any type of traffic right from Plain Old Telephone Service
to Sonet OC-48 traffic, refine the data and transmit. The system is a
time-space-time switching system
|
|
Responsibility
|
·
Verification
environment development in e Language
|
|
Language, Tool
|
Specman
|
|